The present invention relates to an optical disc reproducing apparatus for compact discs (CDs) or the like, and in particular to a voltage controlled oscillator (VCO) circuit included in a PLL (phase-locked loop) circuit for generating a clock signal synchronized with a reproduced signal.
In the field of acoustic devices, digital recording and reproducing systems are now being developed. In order to conduct recording and reproducing data with high density and high fidelity, these systems convert an audio signal to a digital signal by using the PCM (Pulse Code Modulation) technique, record the digital signal on a recording medium such as a disc or magnetic tape, and reproduce the recorded digital signal.
A disc reproducing apparatus for reproducing data from the disc rotates the disc by a motor with CLV (Constant Linear Velocity) or CAV (Constant Angular Velocity), using a motor control circuit.
FIG. 5 is a block diagram of a conventional disc reproducing apparatus. By conducting linear tracking from the inner track side to the outer track side of a disc 15 rotated by a disc motor 16, an optical pickup device 9 reads data recorded on the disc 15 as a reproduced signal and converts it into a current signal.
The data (current signal) thus read is supplied to an amplifier 10. The amplifier 10 converts the current signal to a wideband voltage signal (hereafter referred to as RF signal), and supplies the wideband voltage signal to a data slice circuit 17. The data slice circuit 17 converts the output voltage signal (the reproduced signal) of the amplifier 10 to a binary signal, and supplies the binary signal to a PLL (Phase Locked Loop) circuit 18 and a data processing circuit 11 as an EFM (Eight to Fourteen Modulation) signal. The PLL circuit 18 generates a clock signal PLCK in accordance with a change of data reproduction velocity, on the basis of the binary output signal generated by the data slice circuit 17. The data processing circuit 11 separates a synchronizing signal from the EFM signal, and conducts an EFM demodulation to separate the EFM signal into a 32-symbol data component including parity data P and Q, and a sub-code component. The EFM demodulated data, i.e. reproduced data, is written into a memory (not shown) from the data processing circuit 11, by using a clock signal PLCK generated by the PLL circuit 18. The data written into the memory is read out from the memory with a system reference clock signal XCK generated by using a crystal resonator, and thus the time axis variation caused by the motor is corrected. The data read out from the memory is subject to error correction, and the corrected data is outputted as 16-bit digital data.
The control of the reproduction velocity is conducted by a system controller 20. The system controller 20 generates a reproduction velocity control HS. This HS signal specifies the reproduction velocity, for example, a general reproduction velocity (referred to as unity time velocity) or a velocity equivalent to twice the reference velocity (referred to as double velocity). The reproduction velocity has become increased up to over-forty times the reference velocity in recent technology. The control signal HS is supplied to the data processing circuit 11 and a motor control circuit 19 to change the processing velocity and the disc reproduction velocity to desired velocities. The control signal HS is also supplied to the data slice circuit 17. In according with the control signal HS, the data slice circuit 17 changes the control frequency band so as to correspond to the reproduction velocity.
The PLL circuit includes a VCO circuit for generating an output signal and a phase-locked loop (PLL section). The PLL section detects a phase difference between a signal obtained by applying frequency division to the output signal of the VCO circuit so as to reach a predetermined low frequency and a reference signal of a fixed frequency and supplies a control voltage corresponding to the phase difference to the VCO circuit. In other words, the PLL section controls the output signal of the VCO circuit until such a phase-locked state that the signal obtained by applying frequency division to the output signal of the VCO circuit coincides in phase with the reference signal is reached. The PLL section has a loop filter for converting a signal (current) corresponding to the phase difference to the control voltage.
FIG. 6 shows a block diagram of a conventional VCO circuit of type of a delay line ring oscillator used in general within semiconductor integrated circuits (LSIs) of CMOS structure. A reference block (first delay cell array) is formed of n delay cells 5 connected in series to each other. An oscillation block (second delay cell array) forming a ring oscillator includes, for example, four delay cells 5 connected in series to each other.
FIG. 7A shows an example of a circuit of each of the delay cells 5 used in the first delay cell array and the second delay cell array of the VCO circuit shown in FIG. 6. As shown in FIG. 7A, each of the delay cells used in the VCO circuit shown in FIG. 6 is formed of a transfer gate 1 and an inverter 2. The transfer gate 1 is formed of a P channel (P-ch) MOS transistor 1p and an N channel (N-ch) MOS transistor 1n. The P channel MOS transistor 1p is connected in parallel with the N channel MOS transistor 1n, and the inverter is connected in series to the source-drain paths of the MOS transistors.
FIG. 7B shows an equivalent circuit of the delay cell circuit shown in FIG. 7A. The equivalent circuit includes a variable resistor, an inverter connected in series with the variable resistor, and a capacitor. The capacitor is connected at one end to the junction of the variable resistor and the inverter, and at the other end to ground.
As shown in FIG. 7C, a first control voltage DCV is inputted to the gate of the P-channel MOS transistor 1p of the delay cell 5 in the reference block, and an input signal CV is inputted to the gate of the N-channel MOS transistor in of the delay cell 5 in the reference block. A reference clock signal is inputted to the input terminal of the reference block, and a delayed signal fout (delayed clock signal of the inputted reference clock signal) is outputted from the output terminal of the reference block. The reference clock signal is also inputted to a phase comparator (i.e., a phase detector) 3. The phase comparator 3 compares the phase of the reference clock signal with the phase of the output fout (i.e., delayed clock signal of the inputted reference clock signal) obtained by passing the reference clock signal through the reference block, and supplies the result of comparison to a low-pass filter (LPF) 4. The filter 4 extracts only a low frequency components from the output of the result of phase detection conducted by the phase comparator 3. The low frequency components extracted by the filter 4 is supplied to the gates of the N-channel MOS transistors 1n of the reference block as the input voltage signal CV, as shown in FIG. 7C.
As shown in FIG. 7D, a second control voltage Vin is inputted to the gate of the P-channel MOS transistor 1p of the delay cell 5 in the oscillation block of the ring oscillator, and the input voltage signal CV is also inputted to the gate of the N-channel MOS transistor 1n of the delay cell 5 in the oscillation block. When input voltage signal CV is changed, the on-resistance value of the pair of transistors 1p and in is changed. By a change of the on-resistance value, the time delay of the ring oscillator is changed. By this change, the oscillation frequency of the oscillation block of the ring oscillator is changed.
The output terminal of the oscillation block is connected to the input terminal of an inverter 8, and the output terminal of the inverter 8 is connected to a frequency division circuit 6. The inverter 8 inverts the logic level of the output signal of the oscillation block. After having been level-inverted by the inverter 8, the output signal of the oscillation block is outputted as output signal VOCOout via the frequency division circuit 6. The frequency division circuit 6 divides the output signal of the oscillation block by a frequency division ratio of 1/2.sup.n. The output signal of the inverter 8 is also inputted to an input terminal of the oscillation block.
The reference clock signal is compared in phase with the signal fout (i.e., delayed clock signal of the inputted reference clock signal) obtained by passing the reference clock signal through the reference block. The voltage signal CV obtained by removing high frequency components from the result of phase comparison is inputted to the gates of the N-channel MOS transistors 1n in the reference block. The voltage signal CV is controlled so that the time delay of the reference block may coincide with the phase of the reference clock signal. This is called phase-locked state.
When the voltage signal CV in the phase-locked state is inputted as the gate voltage to the gates of the N-channel MOS transistors 1n in the oscillation block and the same value as the first control voltage DCV is inputted as the gate voltage (the second control voltage) Vin to the gates of the P-channel MOS transistors in, then the oscillation block oscillates with a free run frequency ffr=[(the number of delay cells in the reference block) / (the number of delay cells in the oscillation block)].times.(reference clock frequency). Characteristics of the oscillation frequency ffr of the VCO circuit and the input voltage of the second control voltage Vin in are shown in FIG. 8.
The VCO circuit is such a circuit that its free run frequency can be determined by the ratio of the number of delay cells in the reference block to that in the oscillation block when the reference clock is inputted.
The conventional VCO circuit has such a structure heretofore described. In the currently used VCO circuit, the number of delay cells in the reference block and the number of delay cells in the oscillation block are fixed. If the first control voltage DCV is fixed, therefore, only one free run frequency ffr can be obtained for one reference clock. Therefore, as shown in FIG. 8, only such the output signals can be obtained, which have frequencies obtained by applying frequency division of 1/2.sup.n to the oscillation frequency, using a reference clock. Accordingly, in the case where signals of the frequency division ratio other than 1/2.sup.n, a further reference clock must be used.
As described above, only one ratio in the number of delay cells could be set in the conventional technique. For the reproduction velocity of 2.sup.n times such as one time, twice, 4 times, 8 times, 16 times, and 32 times, therefore, it can be coped with by generating a free run frequency with a single reference clock and applying frequency division to the free run frequency. For the reproduction velocity of 12 times, 24 times, and so on, other than 2.sup.n times, however, the free run frequency had to be generated by using different reference clock generators of different oscillation frequencies. In the case where such a frequency that the frequency division ratio is out of 1/2.sup.n is to be obtained in the existing technique, two or more reference clock generators are required. The reference clock generator is typically a crystal resonator which has a high stability and reliability of oscillation frequency, however, it is expensive and raises a problem of cost.